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Computing Hardware Devices Character Codes Mouse Signals Additive Colour Mixing Monitor Raster Scanning Simple Graphics Adaptor 256 Intensity Levels Colour Monitor Disk Drives CD-ROM Serial Port Communications Serial and Parallel Data Transfer Data Structures Sorting Merging Searching Array Stack Queues Linked Lists Binary Trees Data Files Fixed Length Record Sequential Files Indexed Sequential Files Random Access Hash Tables Locating Individual Records Check Digits Parity Error Checking Cyclic Redundancy Check Computer Systems Computer Hardware Configuration Computer Operating System Local Area Networks Wide Area Network UK Telephone System Data Handling Manual Data Handling System Computer Data Handling System Data and Information Data Entry and Verification Data Validation Methods of Processing Data Data Security - Backups System Development Stages of System Development System Flowcharting Processing Strategy File Management System Computer Hardware Computer Software Computer Programming Programming Structure Constant Values Data Types Data Strings Working with Character Strings Conditional Branching Select...Case Statement Block For...Next Loop Do...Until Loop Procedures Binary Numbers Simple Decimal To Binary Simple Binary to Decimal Decimal To Binary Binary to Decimal Decimal to Octal Octal to Decimal Decimal to Hexadecimal Hexadecimal to Decimal Binary Arithmetic Sign and Magnitude One's Complement Numbers Two's Complement Numbers Decimal to BCD Binary Addition Binary Subtraction Floating Point Binary Numbers Number Systems Addition Subtraction Multiplication Division Types of Numbers Further Addition Further Subtraction Further Multiplication Further Division Directed Numbers Finding Next Number in a Sequence Temperature Conversion Application Matrices Addition Matrices Multiplication
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Digital Techniques Logic Gates 1 Simple OR Logic Function Simple AND Logic Function AND Gate Function OR Gate Function NAND Gate Function NOR Gate Function NOT Gate Function Exclusive OR Gate Function Equivalent Exclusive OR Circuit OR Function from NAND Gates Mixed Logic Analysis 1 Logic Analysis 2 Logic Gates 2 AND Gate OR Gate NOT Gate NAND Gate NOR Gate EXCLUSIVE OR Gate Equivalent OR Gate Equivalent NAND Gate Logic Families DL (Diode Logic) DTL (Diode-Transistor Logic) TTL (Transistor-Transistor Logic) ECL (Emitter Coupled Logic) I2L (Integrated Injection Logic) MOS (Metal Oxide Semiconductor Logic) CMOS (Complementary MOS) Flip Flops NAND RS Flip-flop NOR RS Flip-flop Clocked RS Flip-flop D Type Flip-flop T Type Flip-flop Master Slave Flip-flop JK Flip-flop Combinational Logic Half Adder Full Adder Parallel Adder 2-4 Line Binary Decoder Decimal to BCD Encoder Binary Multiplexer Data Masking Adding a Data Parity Bit Counters Bistable or Flip Flop Clocked R,S Flip Flop D Type Data Latch Divide by Two Counter Divide-by-Four Counter 4-Bit Binary Counter Counting Ripple Counter Up/Down Counter Divide By 7 Counter Synchronous Up Counter Synchronous Down Counter Shift Registers Right Shift Register Left Shift Register Parallel Load Shift Register Logic Interfacing Logic Buffer Stage Bipolar Transistor Driver CMOS to TTL Logic Interface Clock Pulse Generator Monostable Boolean and DeMorgan's Boolean Postulates Commutative and Associative Rules Identity Absorption and Negating Rules Distributive Rules De Morgan's Theorems Simplifying using Boolean Theorem's Simplifying using DeMorgan's Theorem's Data Analysis Frequency Distribution Standard Deviation Pie Chart Probability Tree Probability Addition Law Probability Multiplication Law Quartiles Cumulative Frequency, Box Plot Continuous Even Distribution Sampling Theory Correlation Analysis Moving Average Seasonality
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Microprocessors Micro-Computer Basic Micro-Computer Micro-Computer Architecture Microprocessor Block Diagram Data/Address Bus Microprocessor Data Bus Microprocessor Address Bus Memory Addressing Memory Cell Addressing Chip Select and Addressing A.L.U Logic Unit Accumulator Clock and Reset Microprocessor Clock Microprocessor Reset Circuit Instructions and Control Instruction Register Instruction Decoder Control Signals Chip Select Memory Cells Transistor Switch Multi-Emitter Transistor Read/Write Sense Amplifier Bipolar Memory Cell Microprocessor Memory Read Only Memory Random Access Memory Addressing Modes Immediate Addressing Implied Addressing Absolute Addressing Offset or Relative Addressing Zero Page Addressing Absolute Indexed Addressing Zero Page Indexed Indirect Addressing Indexed Indirect Addressing Indirect Indexed Addressing Instructions Set 1 LDA Load the Accumulator STA Store Accumulator in Memory ADC Add with Carry AND Logical AND ORA Inclusive OR with Accumulator EOR Exclusive OR CMP Compare Accumulator SBC Subtract with Carry LDX Load the X Register LDY Load Y Register STX Store X in Memory STY Store Y in Memory Instructions Set 2 CPX Compare to X Register CPY Compare to Y Register DEC Decrement Memory INC Increment Memory ASL Arithmetic Shift Left LSR Logical Shift Right ROL Rotate Left One Bit ROR Rotate Right One Bit BIT Test Accumulator With Memory Bits JMP Jump to Address JSR Jump to Subroutine NOP No Operation Performed Instructions Set 3 Branching Clear Flags BRK Break DEX Decrement X Register INX Increment X Register DEY Decrement Y Register INY Increment Y Register RTI Return from Interrupt Push Register Contents Pull Register Contents RTS Return from Subroutine Set Status Register Flags Transfer between Registers
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